1. Field of the Invention
This invention relates to a method of forming contact holes in a semiconductor substrate and simultaneously in an electrode formed on the substrate.
2. Description of the Related Art
In general, to produce a semiconductor element, a second conductive type impurity is implanted into a first conductive type semiconductor substrate, and then diffused in it, thereby forming impurity regions. These impurity regions serve as active regions, passive regions, and/or resistor elements
In a field effect transistor, the impurity regions are used as a source region and a drain region Further, an insulation layer of a predetermined pattern is formed on the substrate, for defining an element-forming region. A thin gate oxide layer is formed on the element-forming region, a gate electrode is formed on the oxide layer, and an interstage insulation layer is formed on the resultant structure. A wiring layer is formed on the interstage insulation layer, and connected to the electrode through a contact hole formed in the interstage layer.
The upper surface of the interstage insulation layer can be leveled or flattened by etch back method developed in recent years, so that a wiring layer formed thereon has no stepped portions, thereby preventing the wiring layer from being disconnected and hence enhancing the reliability of the semiconductor element
The interstage insulation layer, however, does not have a uniform thickness since it has a flat upper surface For example, that portion of the layer which extends between the upper surface of the layer and that of the substrate is thicker than that portion of the same which extends between the upper surface of the layer and that of the electrode formed above the substrate.
Now, a conventional method of forming contact holes of a field effect transistor will be explained with reference to FIG. 1A-1E. As is shown in FIG. 1A, a plurality of element-forming regions 3 are defined in a first conductive type (e.g. p-type) silicon substrate 1 by forming a selective oxide layer 2 for isolating elements on the substrate 1. The element-forming regions 3 each have a surface region in which a second conductivity type (e.g. n-type) impurity difference region as a source region 101.sub.1 and a second conductivity type impurity diffused region as a drain region 102.sub.2 are formed. Gate oxide layers 4, gate electrodes 5, and an interstage insulation layer 6 are formed on and above the element forming regions 3. The upper face of the layer 6 is leveled or flattened by etch back method, on which a positive-type resist layer 7 is formed, as is shown in FIG. 1B. A mask 8 is placed over the layer 7, and ultraviolet light 9, indicated by the arrows in FIG. 1B, is applied to the layer 7 through the mask 8 by means of an aligner (not shown). Then, the layer 7 is developed, thereby forming openings 10.sub.1 and 10.sub.2 for impurity diffused regions and an opening 11 for a gate electrode. Subsequently, as is shown in FIG. 1D, the interstage insulation layer is etched by RIE (Reactive Ion Etching) with the use of the resist layer 7 as a mask, thereby forming therein contact holes 12.sub.1 and 12.sub.2 which reach the impurity diffused regions 101.sub.1 and 101.sub.2 and a contact hole 13 which reaches the electrode 5. As can be understood from FIG. 1D, the electrode 5 is also etched to some extent. That is, it has a depression 14 (FIG. 1E). This is because that portion of the interstage insulation layer 6 which extends between the upper surface of the layer and that of the substrate is thicker than that portion of the same which extends between the upper surface of the layer and that of the electrode formed above the substrate.
As is described above, in the conventional method, over-etching occurs when contact holes are simultaneously formed in those portions of the interstage insulation layer which have different thicknesses. To avoid this, it is considered that contact holes for gate electrodes are formed by means of a lithography process different from that in which contact holes for impurity regions are formed. In this case, however, the number of the required processes is increased.
There is another method to avoid over-etching. As is shown in FIG. 2, a resist thin film 15 for preventing over-etching is formed on that portion of the resist layer 7 which is aligned with the thin portion of the interstage insulation layer 6 (in which the contact hole 13 is to be formed). In this method, however, another lithography process is required for forming the resist thin film 15, and further a mask may not be placed in a desired position when the film 15 is formed.